Guided-wave optical interconnects: design methodology development

Technological development is pushing chip performances higher every day. Feature sizes are decreasing, while chip size and data rates continue to rise. Optimal exploitation of this increasing number of faster devices per chip is often hampered by too slow a communication rate between interconnected integrated circuits [3]. The problem has already become a critical bottleneck in some applications with very intensive data traffic, and is expected to proliferate into more mainstream designs as well in the coming years [5]. In order to satisfy this increasing demand for interconnect bandwidth at the PCB level, optical solutions are being widely investigated, as for electrical interconnects a further throughput increase is fundamentally limited by RLC effects [4]. Not hampered by this limit, photonic links intrinsically provide low-power high-bandwidth interconnect; they do not suffer from electromagnetical interference and have potential to scale with future generations of silicon IC’s [3]. The technology of the building blocks of optical interconnects has made immense progress over the past decade. During the past few years, much focus has been put on the use of parallel guided-wave optical interconnects, i.e., transceivers consisting of 2D arrays of VCSELs and photodetectors which are directly flip-chipped onto the processing chip surface, while using waveguide structures for an alignment-tolerant interconnection [2, 6].